View FOD2200_7703889.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

7/7/04 p age 1 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 description the FOD2200 is an optically coupled logic gate that combine an algaas led and an integrated high gain photo detector. the detector has a three state output stage and has a detector threshold with hysteresis. the three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. the hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. the electrical and switching characteristics of the FOD2200 are guaranteed ov er the temperature range of 0? to 85? and a v cc r ange of 4.5 volts to 20 v olts. low i f and wide v cc range allow compatibility with ttl, lsttl, and cmos logic and result in lower power consumption compared to other high speed optocouplers. logic signals are transmitted with a maximum propaga- tion delay of 300 nsec. the FOD2200 is useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments. 8 1 8 1 8 1 7 1 2 3 4 5 6 8 nc anode cathode nc gnd v cc v o shield v e features ? kv/? minimum common mode rejection compatible with lsttl, ttl, and cmos logic wide v cc range (4.5 to 20 v) 2.5 mbd guaranteed over temperature ? ow input current (1.6 ma) three state output (no pullup resistor required) guaranteed performance from 0? to 85? hysteresis safety approvals pending ?ul, csa, vde ? iso = 5kvrms application isolation of high speed logic systems computer-peripheral interfaces microprocessor system interfaces ground loop elimination pulse transformer replacement isolated buss driver high speed line receiver truth table (positive logic) led enable output on h z off h z on l h off l l i f shield v f v cc v o gnd i cc i o + 2 3 8 5 v e 7 6 i e schematic
low input current logic gate optocouplers FOD2200 7/7/04 p age 2 of 14 ?2004 fairchild semiconductor corporation *the initial switching threshold is 1.6ma or less. it is recommended that 2.2 ma be used to permit at least a 20% ctr degradati on guardband. absolute maximum ratings (t a = 25? unless otherwise speci?d) p arameter symbol value units storage temperature t stg -40 to +125 ? operating temperature t opr -40 to +85 ? lead solder temperature (1.6mm below seating plane) t sol 260 for 10 sec ? emitter p eak transient input current ( 1? pw, 300 pps) i f (pk) 1.0 a av erage forward input current i f 10 ma reverse input voltage v r 5.0 v output power dissipation (no derating required up to 85?) p d 45 mw detector supply voltage v cc 0 to 20 v av erage output current i o 25 ma three state enable voltage v e -0.5 to 20 v output voltage v o -0.5 to 20 v output power dissipation (no derating required up to 85?) p d 150 mw recommended operating conditions p arameter symbol min max units f orward input current i f(on) 1.6* 5 ma f orward input current i f(off) 0.1 ma supply voltage, output v cc 4.5 20 v enable voltage, low level v el 0 0.8 v enable voltage, high level v eh 2.0 20 v operating temperature t a 0 +85 ? f an out (ttl load) n 4
7/7/04 p age 3 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 ** typical values at t a = 25?, v cc = 5v, i f(on) = 3 ma unless otherwise speci?d. electrical characteristics (t a = 0? to +85?, v cc = 4.5v to 20v, i f(on) = 1.6ma to 5ma, v eh = 2v to 20v, v el = 0v to 0.8v, i f(off) = 0 ma to 0.1 ma unless otherwise speci?d.) see note 1. individual component characteristics p arameter test conditions symbol min typ** max unit emitter (i f = 5 ma) v f 1.75 v input forward voltage t a =25? 1.40 1.7 input reverse breakdown voltage (i r = 10 ?) b vr 5.0 v input capacitance (pins 2 & 3) (v f = 0, f = 1 mhz) c in 60 pf input diode temperature coef?ient (i f = 5 ma) ? vf/ ? ta -1.4 mv/? detector high level supply current (i f = 5 ma) (i o = open, v e = don? care) v cc = 5.5v i cch 3.5 4.5 ma v cc = 20v 4.0 6.0 low level supply current (i f = 0 ) (i o = open, v e = don? care) v cc = 5.5v i ccl 4.4 6.0 ma v cc = 20v 5.2 7.5 low level enable current v e = 0.4 v i el -0.1 -0.32 ma high level enable current v e = 2.7 v i eh 20 ? v e = 5.5 v 100 v e = 20 v 0.005 250 high level enable voltage v eh 2.0 v low level enable voltage v el 0.8 v switching characteristics (t a = 0? to +85?, i f(on) = 1.6ma to 5ma, i f(off) = 0 to 0.1 ma, v cc = 4.5 to 20v unless otherwise speci?d.) ac characteristics test conditions symbol min typ** max unit propagation delay time to output high level (note 2, 4) t plh 120 300 ns (fig. 1) with peaking capacitor propagation delay time to output low level (note 3, 4) t phl 180 300 ns (fig. 1) with peaking capacitor output rise time (10-90%) (note 5) (fig. 1) t r 80 ns output fall time (90-10%) (note 6) (fig. 1) t f 25 ns enable propagation delay time to output high level (fig. 2) t pzh 40 ns enable propagation delay time to output low level (fig. 2) t pzl 50 ns disable propagation delay time from output high level (fig. 2) t phz 95 ns disable propagation delay time from output low level (fig. 2) t plz 80 ns common mode tr ansient immunity (at output high level) (t a =25?) (i f = 1.6 ma, v oh (min.) = 2.0 v) v cc = 5v (note 7)(fig. 3) |v cm | = 50 v |cm h | 1000 v/? common mode tr ansient immunity (at output low level) (t a =25?) (i f = 0 ma, v ol (max.) = 0.8 v) v cc = 5v (note 8)(fig. 3) |v cm | = 50 v |cm l | 1000 v/?
low input current logic gate optocouplers FOD2200 7/7/04 p age 4 of 14 ?2004 fairchild semiconductor corporation ** typical values at t a = 25?, v cc = 5v, i f(on) = 3 ma unless otherwise stated. transfer characteristics (t a = 0? to +85?, v cc = 4.5v to 20v, i f(on) = 1.6ma to 5ma, v eh = 2v to 20v, v el = 0v to 0.8v, i f(off) = 0ma to 0.1ma unless otherwise speci?d.) see note 1. dc characteristics test conditions symbol min typ** max unit output leakage current (v out > v cc ) (v cc = 4.5 v) (i f = 5 ma) v o = 5.5v i ohh 2.0 100 ? v o = 20v 2.5 500 low level output voltage (v cc = 4.5 v, i f = 0 ma) (v e = 0.4 v, i ol = 6.4 ma) (note 2) v ol 0.33 0.5 v input threshold current (v cc = 4.5 v, v o = 0.5 v, v e = 0.4 v, i ol = 6.4 ma) i ft 1.6 ma logic high output voltage i oh = -2.6 ma v oh 2.4 v cc -1.8 v high impedance state output current v o = 0.4 v, v en = 2 v, i f = 5 ma i ozl -20 ? v o = 2.4 v, v en = 2 v, i f = 5 ma i ozh 20 ? v o = 5.5 v, v en = 2 v, i f = 5 ma 100 ? v o = 20 v, v en = 2 v, i f = 5 ma 500 ? logic low short circuit output current note 10 v o = v cc = 5.5 v, i f = 0 ma i osl 25 ma v o = v cc = 20 v, i f = 0 ma 40 ma logic high short circuit output current note 10 v cc = 5.5 v, i f = 5 ma, v o = gnd i osh -10 ma v cc = 20 v, i f = 5 ma, v o = gnd -25 ma input current hysteresis v cc = 4.5 v i hys 0.03 ma isolation characteristics (t a = -40? to +85? unless otherwise speci?d.) characteristics test conditions symbol min typ** max unit withstand insulation test voltage (r h < 50%, t a = 25?) t = 1 min (note 9) v iso 5000 v rms resistance (input to output) (v i-o = 500 vdc) (note 9) r i-o 10 12 ? capacitance (input to output) (v i-o = 0v, f = 1 mhz) (note 9) c i-o 0.6 pf
7/7/04 p age 5 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 1. the v cc supply to each optoisolator must be bypassed by a 0.1? capacitor or larger. this can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package v cc and gnd pins of each device. 2. t plh - propagation delay is measured from the 50% level on the low to high transition of the input current pulse to the 1.3v level on the low to high transition of the output voltage pulse. 3. t phl - propagation delay is measured from the 50% level on the high to low transition of the input current pulse to the 1.3v level on the high to low transition of the output voltage pulse. 4. when the peaking capacitor is omitted, propagation delay times may increase by 100 ns. 5. t r - rise time is measured from the 10% to the 90% levels on the low to high transition of the output pulse. 6. t f - fall time is measured from the 90% to the 10% levels on the high to low transition of the output pulse. 7. cm h - the maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e., v out > 2.0 v). 8. cm l - the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e., v out < 0.8 v). 9. device considered a two-terminal device: pins 1,2,3 and 4 shorted together, and pins 5,6,7 and 8 shorted together. 10. duration of output short circuit time should not exceed 10 ms. notes
low input current logic gate optocouplers FOD2200 7/7/04 p age 6 of 14 ?2004 fairchild semiconductor corporation fig. 1. t est circuit and w t t a v e f o rm s f o r t plh , t phl , t r a n d t f . fig. 2. t est circuit and waveforms for t t t phz , t pzh , t plz , and t pzl 50 % i f (on) i f (on) 0 ma t plh t phl v oh 1.3 v v ol input i f output v o 7 1 4 5 6 8 FOD2200 gnd v cc 5 v 619 ? input monitoring node pulse gen. t r = t f = 5 ns f = 100 khz 10 % duty cycle v o = 5 v c 2 = 15 pf the probe and jig capacitances are included in c 1 and c 2 . output v o monitoring node v cc r 1 d 1 d 2 5 k ? d 3 d 4 2 3 c 1 = 120 pf r i i f (on) 2.15 k ? 1.6 ma 1.10 k ? 3 ma 681 ? 5 ma all diodes are 1n916 or 1n3064. i f 3.0 v v ol input v e output v o t pzl t plz 1.3 v 0 v v oh ? input v c monitoring node p u l se generator z o = 50 ? t r = t f = 5 ns c l c l = 15 p f including prob e and ji g c apa c itan c e s . v o v cc d 1 d 2 5 k ? d 3 d 4 2 3 d 1-4 are 1n916 or 1n3064. i f s1 s2
7/7/04 p age 7 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 fi g . 3. test circuit and typical waveforms for common mode transient immunit y 50 v output v o * see note 6 . 0 v v oh v ol v o (max.)* v o (min.)* switch at a: i f = 1.6 ma switch at b: i f = 0 ma v cm 7 1 4 5 6 8 FOD2200 0.1 f bypass output v o monitoring node v cc r in 2 3 v ff a b ? + v cm pulse generator v cc gnd FOD2200 data input d1 (1n4150) required for active pull-up driver. 1.1 k ? v cc1 (+5 v) v cc gnd d1 ttl or lsttl figure 4. recommended lsttl to lsttl circuit. figure 6. recommended led drive circuit. figure 5. lsttl to cmos interface circuit. figure 7. series led drive with open collector gate (4.7 k ? resistor shunts i oh from the led). 120 pf 1 2 3 4 8 7 6 5 1 2 FOD2200 data input ttl or lsttl v cc2 (+5 v) up to 16 lsttl loads or 4 ttl loads 1.1 k ? v cc1 (+5 v) data output totem pole output gate v cc gnd 120 pf (optional*) *the 120pf capacitor may be omitted in applications where 500ns propagation delay is sufficient. FOD2200 data input ttl or lsttl 1.1 k ? v cc (+5 v) open collector gate v cc gnd 4.7 k ? 120 pf (optional*) 1 2 FOD2200 data input ttl or lsttl v cc2 (4.5 to 20 v) 1.1 k ? v cc1 (+5 v) data output totem pole output gate v cc gnd cmos v cc2 5 v 10 v 15 v 20 v r l 1.1 k 2.37 k 3.83 k 5.11 k r l 1 2 3 4 8 7 6 5
low input current logic gate optocouplers FOD2200 7/7/04 p age 8 of 14 ?2004 fairchild semiconductor corporation t ypical performance curves i f(on) i f(off) figure 9. output voltage vs. input forward current i f - input forward current (ma) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v o - output voltage (v) 0 1 2 3 4 5 cc i o = -2.6ma v t a = 25 c i o = 6.4ma = 4.5v figure 10. input threshold current vs. ambient temperature t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 input current threshold (ma) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i f (on) i f (off) v cc = 5v, 20v figure 11. logic low output voltage vs. ambient temperature v ol - logic low output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v cc = 4.5v i f = 0 ma i o = 6.4 ma figure 12. logic high output voltage vs. supply voltage v cc - supply voltage (v) 048121620 v oh - logic high output voltage (v) 0 4 8 12 16 20 i o = -2.6 ma t a = 25 c i f i f (on) figure 13. logic high output current vs. ambient temperature t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 i oh - logic high output current (ma) -7 -6 -5 -4 -3 -2 -1 0 v cc = 4.5v i f = 5 ma v o = 2.7v v o = 2.4v figure 8. input forward current vs forward voltage v f - forward voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 i f - forward current (ma) 0.001 0.01 0.1 1 10 100 t a = 85 c t a = 70 c t a = 25 c t a = 0 c t a = -40 c
7/7/04 p age 9 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 t ypical performance curves figure 14. propagation delay vs ambient temperature t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 t p - propagation delay ( s) 60 100 140 180 220 260 v cc t phl , i f t phl , i f = 5 ma = 5v see figure 1. = 1.6 ma t plh , i f = 1.6 - 5 ma t phl , i f c1 (120 pf) peaking capacitor is used. figure 15. rise, fall time vs ambient temperature t f , t r - rise, fall time ( s) 0 40 80 120 160 200 v cc i f t f t r = 5v = 1.6ma = 3 ma
low input current logic gate optocouplers FOD2200 7/7/04 p age 10 of 14 ?2004 fairchild semiconductor corporation note all dimensions are in inches (millimeters) pa ck ag e dimensions (through hole) pa ck ag e dimensions (surface mount) 0.200 (5.08) 0.140 (3.55) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.020 (0.51) min 0.390 (9.91) 0.370 (9.40) 0.270 (6.86) 0.250 (6.35) 3 0.070 (1.78) 0.045 (1.14) 2 41 56 7 8 0.300 (7.62) typ 0.154 (3.90) 0.120 (3.05) 0.016 (0.40) 0.008 (0.20) 15?max pin 1 id. seating plane lead coplanarity : 0.004 (0.10) max 0.270 (6.86) 0.250 (6.35) 0.390 (9.91) 0.370 (9.40) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) typ 0.020 (0.51) min 0.070 (1.78) 0.045 (1.14) 0.300 (7.62) typ 0.405 (10.30) min 0.315 (8.00) min 0.045 [1.14] 32 1 4 567 8 0.016 (0.41) 0.008 (0.20) pin 1 id. pa ck ag e dimensions (0.4"lead spacing) 8 - pin dip 0.200 (5.08) 0.140 (3.55) 0.100 (2.54) typ 0.022 (0.56) 0.016 (0.41) 0.004 (0.10) min 0.390 (9.91) 0.370 (9.40) 0.270 (6.86) 0.250 (6.35) 3 0.070 (1.78) 0.045 (1.14) 2 41 56 7 8 0.400 (10.16) typ 0.154 (3.90) 0.120 (3.05) 0.016 (0.40) 0.008 (0.20) 0?to 15 pin 1 id. seating plane 0.070 (1.78) 0.060 (1.52) 0.030 (0.76) 0.100 (2.54) 0.295 (7.49) 0.415 (10.54)
7/7/04 p age 11 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 carrier tape speci?cations description symbol dimension in mm t ape width w 16.0 ?0.3 t ape thickness t 0.30 ?0.05 sprocket hole pitch p 0 4.0 ?0.1 sprocket hole diameter d 0 1.55 ?0.05 sprocket hole location e 1.75 ?0.10 po ck et location f 7.5 ?0.1 p 2 4.0 ?0.1 po ck et pitch p 12.0 ?0.1 po ck et dimensions a 0 10.30 ?.20 b 0 10.30 ?.20 k 0 4.90 ?.20 cover tape width w 1 1.6 ?0.1 cover tape thickness d 0.1 max max. component rotation or tilt 10 min. bending radius r 30 d 0 p t 2 d 0 1 1 w user direction of feed 0 k b 0 a 0 w e d f p p
low input current logic gate optocouplers FOD2200 7/7/04 p age 12 of 14 ?2004 fairchild semiconductor corporation ordering information example: FOD2200 x marking information x pa ck a ging option s: surface mount lead bend sd: surface mount, tape and reel t: 0.4" lead spacing v: vde 0884 tv: vde 0884, 0.4" lead spacing sv: vde 0884, surface mount sdv: vde 0884, surface mount, tape and reel 1 2 6 4 3 5 de?nitions 1f airchild logo 2d e vice number 3 vde mark (note: only appears on parts ordered with vde option ?see order entry table) 4t wo digit year code, e.g., ?3 5t wo digit work week ranging from ?1 to ?3 6 assembly package code 2200 b yy xx v
7/7/04 p age 13 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200 re?ow pro?le ? peak reflow temperature: 260 c (package surface temperature) ? time of temperature higher than 183 c for 160 seconds or less ? one time soldering reflow is recommended 245 c, 10?0 s ti me (minute) 0 300 250 200 150 100 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 temperature (c) time above 183 c, <160 sec ramp up = 2?0 c/sec 260 c peak
life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. 7/7/04 p age 14 of 14 ?2004 fairchild semiconductor corporation low input current logic gate optocouplers FOD2200

▲Up To Search▲

Price & Availability of FOD2200

	To Download FOD2200 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .